Integrated circuit (IC) dimensions are desired to be constantly scaled down with advancement of technology. Integrated circuits are traditionally patterned according to photolithography technology. However, photolithography technology is reaching limitations for achieving such ever smaller (IC) dimensions into the nanometers range.
For example, line resolution and line edge roughness are limited by the large size of polymer molecules of photo-resist material. In addition, a photo-resist structure that is tall and thin is prone to pattern collapse.
Accordingly, double patterning technology using spacers has emerged to achieve smaller IC dimensions as illustrated in FIGS. 1A, 1B, 1C, 1D, 1E, and 1F. Referring to FIG. 1A, a target layer 102 to be patterned is formed on a semiconductor substrate 104 such as a silicon substrate. A first mask pattern 106 having a first pitch is formed on the target layer 102. Thereafter in FIG. 1B, a layer of spacer material 108 is deposited on exposed surfaces including sidewalls and top surfaces of the first mask pattern 106.
Subsequently referring to FIG. 1C, the spacer material 108 is anisotropically etched to form spacers 110 from the spacer material 108 remaining at sidewalls of the first mask pattern 106. Thereafter referring to FIG. 1D, a second mask material 112 is blanket deposited to fill in the spaces between the spacers 110. Further in FIG. 1E, the second mask material 112 is etched down until the second mask material 112 remaining between the spacers 110 form a second mask pattern 114. Subsequently in FIG. 1F, the spacers 110 are removed such that a final mask pattern is formed from the first and second mask patterns 106 and 114. Such a final mask pattern 106 and 114 is used to pattern the target layer 102 with a pitch that is twice the pitch of the first mask pattern 106 alone or twice the pitch of the second mask pattern 114 alone.
Referring to FIG. 2 for reverse patterning technology using spacers, subsequently after the spacers 110 are formed in FIG. 1C, the first mask pattern 106 is etched away such that just the spacers 110 remain. The remaining spacers 110 are used as the final mask pattern for patterning the target layer 102. Such a final mask pattern 110 has a pitch that is twice the pitch of the first mask pattern 106.
However, such double or reverse patterning technologies of the prior art have high production cost, long production time, and void formation in openings with high aspect ratio. Thus, U.S. Pat. No. 7,312,158 to Miyagawa et al. discloses use of a buffer layer to achieve higher pitch in forming a final mask pattern. However, material to surround such a buffer layer in Miyagawa et al. is deposited using CVD (chemical vapor deposition) which is still prone to void formation in openings with high aspect ratio.
Thus, patterning with fine pitch is desired with prevention of void formation in openings with high aspect ratio.